The present invention relates to generally to integrated circuit packaging technology. More specifically, embodiments of the invention pertain to the use of wire bonding techniques to form stud bumps for wafer-level packages.
Integrated circuits are typically packaged before being used in electronic systems. Integrated circuit (IC) packages protect the integrated circuits from the surrounding environment and provide electrical connections to other components of the electronic systems. In a conventional packaging arrangement, a wafer containing integrated circuits is first singulated into individual chips and then packaged for testing and delivery. This normally includes transporting the wafer (or singulated chips) from a semiconductor manufacturing facility where front-end processes are performed to a separate packaging facility where back-end process are performed to assemble and package the IC.
In contrast, in a wafer-level packaging approach. IC packaging is formed at the wafer level on the wafer prior to singulation. The packages can be manufactured at chip size and at reduced cost compared to standard IC packages. Typical wafer level packages use solder bumps to form electrical connections between the packaged semiconductor die and external devices. Under bump metallurgy (UMB) is formed underneath the solder bumps to minimize metallurgical reactions with the solder and improve the connection.
While a number of commercially successful wafer-level packaging processes have been developed, improved waver level packages are desirable.